1. Field of the Invention
This invention relates to an information processing system, and more particularly to an address decoder having address area expansion capability for use in the information processing system.
2. Description of the Related Art
In a microprocessor, for performing data communication with a plurality of external devices, addresses specifying these respective external devices are outputted. Since these addresses are of encoded general-purpose signal lines, an address decoder is necessary, which causes such functions as waiting and chip-selecting with respect to the designated device according to the specified address area.
Such an address decoder may be one dedicated to each system, or one used as a general-purpose address decoder. It is desired for a system to be architected with as small a number of general-purpose chips as possible. This means that it is necessary to provide a general-purpose chip with a general-purpose address decoder so that the same circuit can provide various functions depending on systems.
To this end, an address decoder having a high degree of freedom is required, which permits address area alteration through register re-writing with the same circuit.
FIG. 1 is a block diagram showing a prior art address decoder. With this address decoder, the entire address area is divided into three division areas without overlap. The system as shown comprises a first address comparator 306 which includes an area boundary register 302 indicating a lower area boundary and a subtracter 304 for subtracting the upper three bits of address data 301 outputted from a processor or the like and the lower area boundary data; a second address comparator 307 which includes an area boundary register 303 indicating an upper area boundary and a subtracter 305 for subtracting the upper three bits of the input address data and the upper area boundary data; an AND gate 311 for taking a logical AND value of the inversion of the carry from the subtracter 304 and the carry from the subtracter 305; and an inverter 309 for inverting the carry from the subtracter 305.
The address data 301 is inputted to each of the first and second address comparators 306 and 307 to be compared in the subtracters 304 and 305, which are 3-bit subtracters, to the contents of the area boundary registers 302 and 303, which are 3-bit registers. The subtracters 304 and 305 subtract the contents of the registers 302 and 303 from the address 301 and generate the sole carries. Thus, if it is found as a result of comparison in the first address comparator 306 that the address 301 is smaller in value than the content of the address register 302, an output of "1" is outputted as an address decoded signal 310. As a result, the lower address area is selected.
If the address 301 is smaller in value than the content of the address register 303, an output "1" is outputted as an address decoded signal 311 from the AND gate 308. In this case, the middle address area is selected.
If the address 301 is larger in value than the content of the address register 303, an output of "1" is provided as an address decoded signal 312 from the inverter 309. In this case, the upper address area is selected.
FIG. 2 shows an example of address area allocation by the address decoder. The entire address space comprises three, lower, middle and upper address areas 401, 402 and 403. Assuming that the address data provided from the processor is of 16 bits, the upper three bits thereof are inputted to the address decoder.
With an address boundary value of "1" being stored in the area boundary register 302, the upper three bits of the boundary address are "1", and an area 0 of the smallest address area is from the address "0000" to the address "1FFF". Likewise, with an address boundary value of "5" being stored in the area boundary register 303, an area 1 is between the registers 302 and 303 and from the address "2000" to the address "9FFF". An area 2 is from the address "A000" to the address "FFFF".
FIG. 3 is a block diagram showing another example of the prior art address decoder. Specifically, FIG. 3 shows an example of area designation by address masking as disclosed in Japanese Patent Application Kokai Publication No. Sho 63-83999.
A mask-gate circuit 502 masks some bits of an address 501 inputted thereto, and thus the address 503 with some bits masked which is outputted to the fail-bit memory 504 designates an address area. By masking given address bits in the above way, it is possible to designate given 2's factorial areas with a restriction that the designation is from the address area frontend. In FIG. 3, designated at 505 is a write-enable (WE) signal, at 506 a data input line (Din), and at 507 a data output line (Dout).
FIG. 4 is a block diagram showing an example of a system using the above address decoders. A general-purpose processor 609 includes a central processing unit (CPU) 601, an address decoder 604 and a wait controller 603 and is connected to a memory device 602 and an input-output (I/O) device 605.
The memory device 602 and I/O device 605, which are accessed from the CPU, are uniformly assigned to the address space of the CPU 601 and, thus, the addressee, i.e., the memory device 602 or the I/O device 605 will know from a chip select signal 608 which is an output of the address decoder 604, that it has been selected. The chip select signal is also inputted to the wait controller 603 in the general-purpose processor 609 so that the wait controller 603 performs wait-controlling of the CPU 601 based on a ready signal 606 outputted therefrom depending on the selected device.
By adopting as the address decoder 604 one of the above address decoders in which the address area is dynamically determined, it is possible to assign the output of the chip select signal to a desired address location without making any change in the internal circuit in the processor 609 which is a peripheral circuit built-in processor. It is thus possible to freely cope with the assignment of the address spaces for the memory device 602 and the I/O device 605 that varies with systems.
The above prior art address decoders have the following drawbacks, respectively.
(1) First prior art example 1 (FIG. 1)
This example is based on the method that two area boundaries are stored in the registers and compared with addresses in the subtracters to decode the area from the comparison results. Therefore, one subtraction has to be done for every decoding, and further a plurality of subtracters are necessary.
Further, with an increase in the number of areas to be decoded, the number of subtracters must be increased accordingly, thus leading to an extremely great increase in the circuit scale. Therefore, the number of areas is often limited. In addition, a common use arrangement is often used for the two area boundaries.
Further, where a 32-bit address is fully to be compared, a 32-bit subtracter should be provided for each area. Subtracters or like circuits are enormously increased with increasing bit number. To suppress the circuit scale, therefore, the bit number of the subtracter is reduced with a sacrifice in the degree of freedom of the address area size.
(2) Second prior art example 2 (FIG. 3)
Since this example is based on the method which uses the address mask only, the start of the address area is always the frontend of address space, and hence the area length is fixed to the 2's factorial address length. In addition, the securing of a plurality of areas results in overlap of the portions of the adjacent areas.
For the above reasons, the degree of freedom of securing areas is extremely low, and the prior art address decoders are therefore hardly suited to the purpose of address decoding.